1. Field of the Invention
The embodiments of the invention generally relate to a system and method for controlling thermal gradients in a silicon wafer during thermal processing.
2. Description of the Related Art
While the use of high temperature ovens for thermal processing of wafers to manufacture advanced integrated circuit chips have been in use for the past few decades or so, the use of rapid thermal processing and the requirement to control the wafer temperature gradients at the process peak temperature within a continuously decreasing processing window is a more recent development, mostly driven by the continuous reduction in the dimensions of the electronic transistors being fabricated in the wafer surface. Economic forces drive both the need to increase function integration within each silicon die and the need to develop new technologies to increase the processing capability of each die in a continuous effort to reduce the die unit cost. As the size of transistors being built on the surface of a silicon wafer decrease well under submicron dimensions the need for fast wafer thermal processing continues and the need for tighter control increases. One particular example of this is the junction anneal where fast thermal processing allows the process to balance the need for thermally activating dopant atoms in the silicon wafer with the need to minimize and optimize the diffusion of the dopant atoms near the channel and the gate.
Rapid thermal processing of silicon wafers is typically done in tools that process one wafer at the time to facilitate wafer heating and cooling through both of the silicon main surface areas. Single wafer processing also facilitates the effort required to control the wafer temperature gradients. However, faster heating ramp rates increase the difficulties to maintain uniform temperature distribution over the functional wafer surface at the desired peak processing temperature of interest. For practical purposes, the wafer thermal gradients can be separated into global thermal gradients and local thermal gradients. Global thermal gradients are dependent mostly on one geometric axis and typically affect the whole wafer, such as, for example radial or axial thermal gradients. Local thermal gradients usually affect only a fraction of the wafer. To facilitate the thermal control over the whole wafer, most of the ovens use heating elements that provide heat flux with angular symmetry relative to the wafer center axis. Since the wafer has more surface/volume ratio at the perimeter most furnace manufacturers provide some capability to tune the heat flux radially and the angular dependency is controlled by either rotating the wafer or with the use of angularly independent heating elements. In some cases, the wafer radial thermal gradient is minimized with the use of a thermal ring around the wafer periphery, as described in U.S. Pat. No. 7,127,367 to Ramachandran et al. This ring is designed to heat and cool at a prescribed rate to control the wafer thermal radial gradients. Radially dependent thermal gradients, with low or no angular dependency are usually caused by the interaction between a radially dependent radiative heat flux provided by the furnace and a radially dependent thermal coupling between the wafer and its surroundings. This type of global thermal gradient, which has an effect on the whole wafer, cannot be resolved by wafer rotation. Another type of global thermal gradient, known as an “axial” gradient, is dependent upon the depth within the wafer in an axial direction of the wafer. Global axial thermal gradients, i.e. axial gradients which are not radially dependent, are usually controlled by rebalancing the radiative energy distribution in the furnace above and below the wafer.
Local thermal gradients within the wafer can be caused by the thermal interaction between the wafer and a support structure used to position the wafer in the oven. Local thermal gradients are usually controlled with the use of open support structures which are designed to present very little obstruction to radiative energy emitted from the internal walls of the oven or processing chamber. For example, as illustrated in FIG. 1, a wafer 10 can be maintained in position during such processing by force of its weight upon a structure 20 having support pins 22 made with materials which have low thermal conductivity like quartz, fused silica, or other material compatible with the process used to treat the silicon wafer. In many tools, fused silica is the material of choice for the fabrication of these support pins because this material has both low thermal conductivity and low thermal expansion coefficient. The low thermal conductivity reduces the thermal coupling between the wafer and the support pins, thus enabling a thermal control capable of maintaining the wafer temperature within a 10° C. thermal window in processes that require heating the wafer to a temperature peak above 1000° C. In parallel, the low thermal expansion coefficient of fused silica is similar to the thermal coefficient of the silicon wafer and results in minimal lateral displacements between the support pins and the wafer during thermal processing to high temperature. Lateral displacements of contact points in the back side of the wafer can create micron size cracks on the wafer bottom surface which can later grow with further thermal treatments and precipitate unacceptable wafer damage and even catastrophic breaking of wafers.
In a conventional arrangement for processing, the wafer is suspended inside an oven 14 using a wafer transport mechanism that holds the wafer using at least three long pins 22, as shown schematically in FIG. 1. The length of each support pin typically is kept in a range of 20 to 80 mm to allow sufficient distance between the wafer and the support structure, thus reducing the exchange of radiative energy between these two objects, while simultaneously increasing the exchange of radiative energy between the bottom surface 28 of the wafer 10 and the oven 14. The structure used to hold the pins that support the wafer is usually too massive to heat and cool at a fast rate and it is expected to remain significantly cooler than the wafer at all times. The diameter of the fused silica pins is kept at or above 1.8 mm, depending on the pin length, to provide a pin with sufficient strength so that a set of three pins can support a 300 mm wafer.
But with the development of new processes with short peak temperature soaks usually shorter than a few seconds, fast ramp rates typically around −25-300° C./second, and continuously shrinking complex structures to create new and more powerful transistor devices, the existing thermal processing window of 10° C. with a peak processing temperature, well above 1000° C., is not sufficient to generate wafers with acceptable yields. This type of rapid thermal processing can be done by moving the wafer inside the oven from a zone of the oven at comparatively low temperature into another zone of the oven at a higher temperature. The oven temperature profile is kept constant at a prescribed temperature distribution. (See, for example U.S. Pat. No. 6,768,084 to Liu et al.)
A typical wafer temperature distribution in a high temperature fast junction anneal process, depicted in FIG. 2, shows the deficiencies of the existing rapid thermal processing technology. Advances in wafer peak temperature characterization allow the precise determination of wafer functional surface temperature to a level better than one degree Celsius. The data thus collected shows that the wafer peak temperature distribution is lower on the regions of the wafer that surround the point where the support pins contact the wafer and do not meet the new requirements to be within a 2° C. thermal window. The data illustrates the shortcomings of the existing rapid processing tools to deliver adequate process temperature control within the wafer surface. The resulting distribution of temperatures within the wafer is also dependent on the radiative properties of the front and rear surfaces of the wafer. As it can be demonstrated that the radiative properties of the wafer are dependent upon the type of structures present at the front (functional) surface of the wafer, it is apparent that different wafers can have temperature distributions which exhibit significant differences due to differences between the structures being fabricated on each wafer.
During thermal processing the wafer interacts strongly with some of the oven internal elements. These interacting elements are shown partially in FIG. 1 and include the silicon wafer 10, the internal heated wall 12 of the oven 14, and the wafer support structure 20. As depicted in FIG. 1, a section of the wafer 10 has been cut away in order to show a location 26 where one of the support pins 22 contacts the wafer 10. While the support structure 20 has many different components, only two of these components are shown here, namely the wafer support pins 22 and the pin holder arms 24. The support pins support the weight of the wafer in a position sufficiently to avoid the wafer from tipping. For ease of illustration, other components of the oven such as heating elements, a thermal ring around the wafer, inlet and outlet gas lines, and external infrastructure are not shown in FIG. 1. While radiative energy exchange is the dominant heat transfer mechanism between all the components described above, heat conduction inside the wafer 10 and each support pin 22 are also important. Some of these other components may also participate on the radiative process that determines the wafer thermal response, but their importance is mostly related to wafer global thermal gradients.
While there are many different thermal profiles that are used in a rapid thermal processing tool, the majority of the processes do involve a preheat ramp to a preset intermediate temperature, a short soak at the intermediate temperature, a fast ramp to the process peak temperature, a prescribed soak time of 0-10 min, and a fast cooling ramp. Since the overall process is done rapidly, the oven must be kept at a relatively constant temperature profile to provide a controlled distribution of radiative energy in the oven hot zone. The preheat ramp and short temperature soak are needed to bring the wafer to an intermediate temperature where the radiative energy transport is the dominant heat transfer mechanism. The soak is needed to let the wafer temperature equilibrate sufficiently to facilitate the required thermal control at the process peak temperature. The wafer fast temperature ramp to the process peak temperature can be done by moving the wafer at a fast and controlled displacement rate between a zone of the oven where it is maintained during the soak and another zone of the oven where the wafer reaches the peak temperature. Both the wafer 10 and the support pins 22 are expected to heat up at similar heating rates, but the rest of the support structure 20, including the pin holder arms 24 do not heat up significantly in the short processing time, mainly because of their significantly larger thermal mass.
The shortcomings of the existing technology are shown by profiling the wafer temperature in a path that goes over the area where the wafer 10 contacts the support pin 22. An example of such temperature distribution is depicted in FIG. 2. The line “DT-w” in FIG. 2 depicts wafer temperatures observed via measurements during a rapid thermal processing (“RTP”) process, such temperatures being observed via measurements of resistance at various points along the front (active) surface of the wafer. The line DT-w indicates the wafer functional surface temperature at the point opposite to the support pin contact point to be about 10° C. cooler than the wafer average temperature. This line also shows the cooling effect from the pin to affect an area of approximately 30 mm in diameter around this contact point. In those areas of the wafer surrounding a support pin 22, the presence of a thermally coupled support pin 22 effectively modifies the transient thermal response of the wafer relative to changes in radiative conditions.
It bears noting that not all the length of the support pin 22 is thermally coupled to the wafer. Only a portion of the length at the top of the pin that is proportional to the support pin 22 thermal conductivity is capable of interacting with the wafer. Since the thermal conductivity of fused silica is the lowest relative to the conductivity of other materials also used in these types of applications, like silicon, silicon carbide or quartz itself, it is understandable that no thermal solutions are possible to minimize the local thermal gradient created by the existing tooling.